(1) Field of the Invention
The present invention relates to split-gate memory cells used in flash EEPROMs (Electrically Erasable Programmable Read Only Memories), and in particular, to a method of forming a floating gate of a split-gate flash self-aligned to a shallow trench isolation (STI).
(2) Description of the Related Art
In the manufacture of split-gate flash memory cells, in particular, appropriate alignment tolerances must be factored into the design in forming floating gates over source regions of the cell. In general, self-alignment techniques are important in VLSI and ULSI (very large and ultra large scaled integrated) fabrication technology since they reduce the difficulties of precise alignment, and allow considerable shrinkage of the device size. A measure of the degree of shrinkage in each new generation of technology is the minimum gate length, for example, in MOS (metal-oxide-semiconductor) devices. At the same time, it is known that in order to assure proper MOS device operation, it is essential to have an overlap between the gate and the source/drain electrodes of the device in mask alignment during device fabrication. The overlap, on the other hand, is governed by the gate length. Thus, source and drain regions might not line up correctly relative to the gate, deposited contacts might not line up perfectly inside contact holes. It is disclosed later in the embodiments of the present invention a method of forming a floating gate self-aligned to shallow trench isolation regions that define the source regions of the cell.
One of the important drivers for increased performance in computers is the higher levels of integration of circuits. This is accomplished by miniaturizing or shrinking device sizes on a given chip. Tolerances play an important role in being able to shrink dimensions on a chip. Self-alignment of various components in a device can help reduce those tolerances and improve packing density of chips. As is known in the art, a split-gate flash memory cell normally has a floating gate, a control gate, source and drain regions, and none of them are usually self-aligned with respect to each other. That is, floating gate is not aligned to the cell isolation regions, nor to the common source line, nor to the control gate, or word line. This is primarily because of the poly oxide process employed in forming the floating gate. As it will be known to those skilled in the art, it is common practice to first form a poly-oxide over a polysilicon layer, and then use it as a hard-mask to etch the polysilicon to form a floating gate. However, the poly-oxide is usually thick and not dimensionally controllable, and hence the alignment of the floating gate to the underlying source region is not precise. It is disclosed later in the embodiments of the present invention a method of aligning the floating gate to the source through a judicious use of an organic antireflective coating (ARC) layer prior to the forming of the poly-oxide. With this method, mis-alignment and hence large tolerances are eliminated, and hence, the memory cell can be substantially reduced in size with the attendant improved packing density and performance.
Over the years, numerous improvements in the performance as well as in the size of memory devices have been made by varying the simple, basic one-transistor memory cell, which contains one transistor and one capacitor. The variations consist of different methods of forming capacitors, with single, double or triple layers of polysilicon, and different materials for the word and bit lines. In general, memory devices include electrically erasable and electrically programmable read-only memories (EEPROMS) of flash electrically erasable and electrically programmable read-only memories (flash EEPROMs). Many types of memory cells for EEPROMs or flash EEPROMs may have source and drains regions that are aligned to a floating gate or aligned to spacers. When the source and drain regions are aligned to the floating gate, a gate electrode for a select transistor is separate from the control gate electrode of the floating gate transistor. Separate select and control gates increase the size of the memory cell. If the source and drain regions are aligned to a spacer formed after the floating gate is formed, the floating gate typically does not overlie portions of the source and drain regions. Programming and erasing performance is degraded by the offset between the floating gate and source and drain regions.
A method of forming a conventional split-gate flash memory cell is shown in FIG. 1a where a layer of gate oxide (30) is thermally grown over substrate (10). Next, a first polysilicon layer (40) is formed followed by the deposition of nitride layer (50). A photoresist layer (60) is then spun over the substrate and then patterned with a floating gate pattern as shown in FIG. 1b, which in turn, is etched into the nitride layer (50) a s shown in FIG. 1c. The photoresist layer, which is no longer needed, is removed. Next, the first polysilicon that is exposed in the pattern openings in the nitride layer is oxidized to form polyoxide (45) as shown in FIG. 1d. Subsequently, the nitride layer is removed where now polyoxide (45) serves as a hard mask to remove all the first polysilicon portions except those that are cover ed by the polyoxide (FIG. 1e). As is well known in the art, this is usually accomplished by main etch followed by over-etch. It is at this etching step that the corner edge (47) is usually rounded off, as seen in FIG. 1e, which is not desirable for achieving precise alignment of the floating gate with the underlying source region. It will be shown later in the embodiments of this invention that by using an ARC layer, a much better self-alignment can be achieved than with the conventional poly-oxide hard-mask. Also, the sharpness of corner edge (47) can be improved such that charge transfer between substrate (10) and floating gate (40), and then the charge transfer between the floating gate and control gate, (80), is fast. The control gate is next formed by depositing a second polysilicon layer over intergate layer (70), also known as interpoly, which separates the two polysilicon layers, namely, the floating polygate and the control polygate. The completed split-gate cell structure is shown in FIG. 1f. 
In prior art, various techniques have been employed to form split-gate flash memory cells, and also to achieve self-alignment between the floating gate and the source of the cell. Thus, in U.S. Pat. No. 5,330,938, Camerlenghi discloses a method of making non-volatile split gate EPROM memory cell and self-aligned field insulation. Here, the cell comprises a substrate with diffusions of source and drain separated by a channel area a floating gate superimposed over a first part of said channel area and a control gate formed by a first and a second polysilicon strip, respectively, a cell gate oxide between said floating gate and said first part of the channel area, a transistor gate oxide between said control gate and a second part of the channel area, an interpoly oxide between said floating gate and said control gate and a layer of dielectric filler. By means of a process which provides for self-aligned etchings of layers of polysilicon and of oxides there is obtained a floating gate and a control gate self-aligned with one another and with the diffusions of source and drain, as well as with the first oxide.
In another U.S. Pat. No. 5,688,705, Bergemont discloses a method for reducing the spacing between the horizontally adjacent floating gates of a flash EPROM array. The spacing between the horizontally-adjacent floating gates of a xe2x80x9cT-shapedxe2x80x9d flash electrically programmable read-only-memory (EPROM) array is reduced beyond that which can be photolithographically obtained with a given process by covering the layer of polysilicon that forms the floating gates with two sacrificial layers, exposing ships of the polysilicon layer with a standard photolithographic process, forming spacers that protect a portion of the exposed polysilicon layer and then etching the layer of polysilicon that remains exposed.
Hsieh, et al., on the other hand, teach in U.S. Pat. No. 6,017,795 a method of fabricating buried source to shrink cell dimension and increase coupling ratio in split-gate flash. The source line is formed in a trench in the substrate over the source region. The trench walls provide increased source coupling and the absence of gate bird""s beak with the trench together shrink the cell size.
In still another U.S. Pat. No. 6,046,086, a method is provided for forming a split-gate flash memory cell having reduced size, increased capacitive coupling and improved data retention capability. In it, Lin, et al., also show a split-gate cell with appropriate gate oxide thicknesses between the substrate and the floating gate and between the floating gate and the control gate along with an extra thin nitride layer formed judiciously over the primary gate oxide layer in order to overcome the problems of low data retention capacity of the floating gate and the reduced capacitive coupling between the floating gate and the source of prior art.
In U.S. Pat. No. 5,950,087, a different method is provided by Hsieh, et al., for forming a common self-aligned source line in order to reduce the number of surface contacts and at the same time alleviate the field oxide encroachment into a memory cell area. Thus, the size of the split-gate flash memory is substantially reduced on both accounts. This is accomplished by forming a buffer polysilicon layer over the floating gate to serve as an etch stop to protect the first poly-oxide of the floating gate during the self-aligned source etching.
The present invention discloses a much different method of forming a self-aligned floating gate through the use of a layer different from the commonly used poly-oxide layer, as described later in the embodiments of the invention.
It is therefore an object of this invention to provide method of forming a floating gate self-aligned to shallow trench isolation (STI) in an EEPROM.
It is another object of the present invention to provide a method of forming a floating gate self-aligned to STI through a new use of an anti-reflective coating (ARC).
It is still another object of the present invention to provide a method of forming a floating gate self-aligned to STI through a new use of a low-viscosity material.
It is yet another object of the present invention to provide a method of forming a self-aligned floating gate in order to affect a reduction in the size of a split-gate flash memory cell.
These objects are accomplished by providing a semiconductor substrate having shallow trench isolation (STI) regions formed therein and active regions defined; forming a gate oxide layer over said substrate; forming a first polysilicon layer over said gate oxide layer; forming an anti-reflective arc coating (ARC) layer over said first polysilicon layer; partial etching of said ARC layer until portions of underlying said first polysilicon layer over said STI regions are exposed; partial etching of said exposed portions of said first polysilicon layer until underlying said STI regions are exposed, thus leaving said active regions in said substrate protected by said ARC layer; removing said organic ARC layer; forming a nitride layer over said substrate; patterning said nitride layer to form floating gate regions self-aligned to said STI regions until portions of said first polysilicon layer over said active regions are exposed; forming a poly-oxide by oxidizing said exposed portions of said first polysilicon layer; removing said nitride layer; etching remaining said first polysilicon layer by using said poly-oxide as a hard-mask; forming an interpoly oxide layer over said substrate, including over said poly-oxide; forming a second polysilicon layer over said interpoly oxide layer; patterning said second polysilicon layer to form , a control gate in completion of said split-gate of said invention.
These objects are accomplished further by providing a semiconductor substrate having shallow trench isolation (STI) regions formed therein and active regions defined; forming a gate oxide layer over said substrate; forming a first polysilicon layer over said gate oxide layer; forming a low-viscosity organic layer over said first polysilicon layer; partial etching of said low-viscosity organic layer until portions of underlying said first polysilicon layer over said STI regions are exposed; partial etching of said exposed portions of said first polysilicon layer until underlying said STI regions are exposed, thus leaving said active regions in said substrate protected by said low-viscosity organic layer; removing said low-viscosity organic layer; forming a nitride layer over said substrate; patterning said nitride layer to form floating gate regions self-aligned to said STI regions until portions of said first polysilicon layer over said active regions are exposed; forming poly-oxide by oxidizing said exposed portions of said first polysilicon layer; removing said nitride layer; etching remaining said first polysilicon layer by using said poly-oxide as a hard-mask; forming an interpoly oxide over said substrate, including over said poly-oxide; forming a second polysilicon layer over said interpoly oxide; patterning said second polysilicon layer to form a control gate in completion of said split-gate of said invention.